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switch case within process vhdl

By Tough TurtleTough Turtle on Apr 24, 2020 
p_CASE : process (r_VAL_1, r_VAL_2, r_VAL_3)
    variable v_CONCATENATE : std_logic_vector(2 downto 0);
  begin
    v_CONCATENATE := r_VAL_1 & r_VAL_2 & r_VAL_3;
     
    case v_CONCATENATE is
      when "000" | "100" =>
        r_RESULT <= 0;
      when "001" =>
        r_RESULT <= 1;
      when "010" =>
        r_RESULT <= 2;
      when others =>
        r_RESULT <= 9;
    end case;
     
  end process;

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case vhdl

By Alert AngelfishAlert Angelfish on May 30, 2021 
case SEL is
  when "01" =>   Z <= A;
  when "10" =>   Z <= B;
  when others => Z <= 'X';
end case;

Source: www.ics.uci.edu

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